1) Field of Invention
The invention relates to methods of forming high-density flash memory arrays and the resulting high density flash memory arrays.
2) Description of the Prior Art
In the NOR-type memory cell, the polysilicon memory select gate is connected to a word line, one floating gate-side diffusion is connected to a source line, and the other diffusion is connected to a bit line. Word lines run parallel to the source lines and perpendicular to the bit lines. Better density may be achieved when the source lines are rotated to run parallel to the bit lines, and then combined into single lines. Such high density flash memory arrays, having interchangeable bit lines/source lines between adjacent cells, have been described in previous works such as U.S. Pat. No. 5,654,917 (IBM) to S, Ogura et al, and U.S. Pat. No. 5,278,439 to Yueh Y. Ma: "Self-aligned dual-bit split gate (DSG) flash EEPROM cell".
Referring to FIG. 1, a schematic of the high density array described in U.S. Pat. No. 5,654,917 is shown. The memory cell is a planar two polysilicon structure, and source and drain regions are interchangeably shared between adjacent cells on the same word line (WL0 or WL1, for example). Read access for this array operates using the current sensing "domino" method or the "skippy domino" method, in which read is limited to serial applications. The bit line to be sensed (one of B0-B4) is always the line that is closest to the selected floating gate. The line on the opposite side of the word gate is then grounded. All other bit lines are pre-charged to the same voltage as the word line high voltage (VDD). Sensing begins when the word line is raised to VDD. In this approach, if the selected cell has a low threshold and the bit line drops below VDD-Vt, then the adjacent cell which shares the same bit line may also start to conduct, depending on its threshold state, and interfere with the bit line signal. Thus, sensing must be completed before the bit line drops beyond VDD-Vt. This stipulation renders sensing of multi-level thresholds difficult, if not impossible.
An array from Yueh Y. Ma's "Self-aligned dual-bit split gate (DSG) flash EEPROM cell" is shown in FIG. 2A. A cross-section of 2A (2B--2B) is shown in FIG. 2B. The memory cell is a triple polysilicon split gate structure in which the floating gate 22 is polysilicon level 1, the control gate 26 is polysilicon level 2, and the word select gate 30 is polysilicon level 3. Source/drain diffusions 40 are placed every two floating gates apart, thus improving density over the conventional cell, which has separated source and drain regions. Although two floating gates share the same word gate, source and drain regions, read and/or program to a single floating gate is possible because control gates are separated. Above each of the floating gates lies a control gate which controls the voltage of the individual floating gate by capacitance coupling. The control lines run parallel to the source/drain. Some of the disadvantages of the DSG cell are high program voltages of about 12V and also high voltages during read. A high control gate voltage of 12V is required during read operation when one of the floating gates is being accessed in order to mask out the effects from the other floating gate. Adjacent cells which may share the same diffusion or control gate voltages will be effectively disabled from the operation by suppressing the other floating gate with a very low .about.0 control gate voltage. The same kind of over-ride and suppress techniques are used during program in order to target a single floating gate cell. In this way, program and read operations can be performed on the high density, self-aligned dual-bit split gate flash/EEPROM cell. However, the highest density ideal memory will be one that not only uses silicon area effectively, but also implements multi-level storage.